Phase-detectors are logic circuits used to generate "pump-up" and "pump-down" signals to control a charge-pump circuit in a clock and data recovery PLL. Phase-detectors are also used to generate recovered data. As the operating speed of clock and data recovery circuits increases, the design of voltage-controlled oscillators (VCOs) becomes more complicated. High speed VCOs also consume more power.
Conventional phase-detector architectures use a full-rate clock. Some conventional architectures use multiple phases of a lower-rate clock but have non-linear characteristics or reduced linear range.
Referring to FIG. 1, a circuit 10 illustrating a conventional approach for implementing a phase-detector based on a "full-rate" clock is shown. A full-rate clock is defined as a clock signal having a frequency (measured in Hertz) that is numerically equal to the data rate (measured in bits/second). The circuit 10 comprises a flip-flop 12, a flip-flop 14, an XOR gate 16 and an XOR gate 18. The XOR gate 16 generates a "pump-up" signal in response to a signal DATA and clocked-data input. The clocked-data input is generated by the flip-flop 12 in response to the signal DATA. The XOR gate 18 generates a "pump-down" signal using the output of the flip-flops 12 and 14. The circuit 10 illustrates a phase-detector having linear phase-difference vs. gain characteristics.
The circuit 10 requires a full-rate clock which is more difficult to generate than a slower rate clock. In a PLL application, such a phase-detector would require a VCO (not shown) to run at the full-rate. As a result, the VCO would consume more power and would be more difficult to design than a VCO running at a slower rate.
Referring to FIG. 2, a circuit 30 illustrating a second approach for implementing a phase detector is shown. The circuit 30 generally comprises a latch 32, a latch 34, an AND gate 36, an XOR gate 38, a NAND gate 40 and a NAND gate 42. The circuit 30 illustrates one of "n" parallel structures in an "n" bit parallel phase detector. The XOR gate 38 presents the pump-up signal PUn and the NAND gate 42 presents the pump-down signal PDn. The pump-down signal PDn is generated in response to the pump-up signal PUn through the latch 34.
The circuit 30 relies on pump-up signal PUn for the generation of the pump-down signal PDn. As the phase-difference between the clock and the signal DATA decreases, the pump-up signal PUn becomes narrower and may fail to trigger the pump-down latch 34, which may cause the pump-down signal PDn not to trigger in some applications. As a result, a non-linear operation may occur.